 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : or1200_immu_top_1
Version: F-2011.09-SP2
Date   : Tue Apr 15 00:19:51 2014
****************************************

Operating Conditions: tt1p05v25c   Library: saed32rvt_tt1p05v25c
Wire Load Model Mode: enclosed

  Startpoint: dis_spr_access_scnd_clk_reg
              (rising edge-triggered flip-flop clocked by clk)
  Endpoint: spr_dat_reg_reg[17]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  or1200_immu_top_1  8000                  saed32rvt_tt1p05v25c
  or1200_immu_tlb    ForQA                 saed32rvt_tt1p05v25c

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   2.00       2.00
  clock network delay (propagated)                        0.23       2.23
  dis_spr_access_scnd_clk_reg/CLK (DFFARX1_RVT)           0.00       2.23 r
  dis_spr_access_scnd_clk_reg/QN (DFFARX1_RVT)            0.08       2.32 r
  U114/Y (NAND2X0_RVT)                                    0.10       2.42 f
  U153/Y (INVX1_RVT)                                      0.14       2.55 r
  or1200_immu_tlb/spr_cs (or1200_immu_tlb)                0.00       2.55 r
  or1200_immu_tlb/U3/Y (INVX1_RVT)                        0.16       2.72 f
  or1200_immu_tlb/U2/Y (INVX1_RVT)                        0.15       2.87 r
  or1200_immu_tlb/U30/Y (AO22X1_RVT)                      0.09       2.96 r
  or1200_immu_tlb/U29/Y (AO22X1_RVT)                      0.08       3.04 r
  or1200_immu_tlb/spr_dat_o[17] (or1200_immu_tlb)         0.00       3.04 r
  U28/Y (AO22X1_RVT)                                      0.08       3.12 r
  spr_dat_reg_reg[17]/D (DFFARX1_RVT)                     0.04       3.16 r
  data arrival time                                                  3.16

  clock clk (rise edge)                                  52.00      52.00
  clock network delay (propagated)                        0.10      52.10
  clock uncertainty                                      -0.20      51.90
  spr_dat_reg_reg[17]/CLK (DFFARX1_RVT)                   0.00      51.90 r
  library setup time                                     -0.02      51.87
  data required time                                                51.87
  --------------------------------------------------------------------------
  data required time                                                51.87
  data arrival time                                                 -3.16
  --------------------------------------------------------------------------
  slack (MET)                                                       48.71


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